1. Field of the Invention
The present invention relates to a substrate for a liquid crystal display device used for a display portion of a notebook-size personal computer, a wall-mounted television or the like, a liquid crystal display device provided with the same, and a manufacturing method of the same.
2. Description of the Related Art
In recent years, the market scale of an active matrix type color liquid crystal display device in which each pixel is provided with a thin film transistor (TFT) as a switching element, has been greatly expanded, and the production quantity has been rapidly increased. On the other hand, as the market scale of the liquid crystal display device is expanded and the production quantity is increased, the product unit price tends to lower. Thus, it is desired to provide a more efficient manufacturing process and to reduce the manufacture cost.
Here, a conventional manufacturing method of a TFT substrate in which TFTs are formed will be described. FIGS. 32A to 32F are process sectional views showing the conventional manufacturing method of the TFT substrate. In FIGS. 32A to 32F, left parts show sections in the vicinity of a TFT, and right parts show sections in the vicinity of a storage capacitor. First, a chromium (Cr) film having a thickness of 150 nm is formed on the whole surface of a transparent glass substrate 110, and pattering is carried out using a first photomask, so that a gate electrode 112 and a storage capacitor bus line 114 are formed. Next, a silicon nitride film (SiN film) which becomes an insulating film (gate insulating film) 116 and has a thickness of 400 nm, an amorphous silicon (a-Si) layer 118 having a thickness of 15 nm, and a SiN film 120 having a thickness of 120 nm are continuously formed on the whole surface of the gate electrode 112 and the storage capacitor bus line 114 by using a plasma CVD apparatus (see FIG. 32A).
Next, a resist is coated on the whole surface of the substrate, and back exposure is carried out from the back surface side (the lower part in the drawing) of the glass substrate 110 while the gate electrode 112 is used as a mask, and further, exposure using a second photomask is carried out, so that a resist pattern (not shown) is formed on the gate electrode 112 in a self-aligning manner. Next, etching is carried out while the obtained resist pattern is used as an etching mask, so that a channel protection film 122 is formed on the gate electrode 112 as shown in FIG. 32B.
Next, as shown in FIG. 32C, an n+a-Si layer 124 having a thickness of 30 nm is formed on the whole surface of the channel protection film 122 by using a plasma CVD apparatus. Next, as shown in FIG. 32D, a titanium (Ti) layer having a thickness of 20 nm, an aluminum (Al) layer having a thickness of 50 nm, and a Ti layer having a thickness of 80 nm are formed on the whole surface of the n+a-Si layer 124 in this order by a PVD method using a sputtering apparatus, so that a drain metal layer 126 is formed.
Next, the drain metal layer 126, the n+a-Si layer 124 and the a-Si layer 118 are patterned using a third photomask, so that a drain bus line (not shown), a drain electrode 130, a source electrode 132, a storage capacitor electrode 128 and an active semiconductor layer 134 are formed as shown in FIG. 32E. In an etching treatment in the patterning, the channel protection film 122 functions as an etching stopper, and the a-Si layer 118 (active semiconductor layer 134) as a lower layer thereof is not etched but remains.
Next, as shown in FIG. 32F, a SiN film having a thickness of 300 nm is formed on the whole surface by using a plasma CVD apparatus, so that a protection film 136 is formed. Next, a fourth photomask is used to pattern the protection film 136, so that a contact hole 138 on the source electrode 132 and a contact hole 140 on the storage capacitor electrode 128 are formed. Next, an ITO (Indium Tin Oxide) layer having a thickness of 70 nm is formed on the whole surface, and a fifth photomask is used to carry out patterning, so that a pixel electrode 142 is formed. The TFT substrate is completed through the above process.
Incidentally, there are references as follows: patent document 1: JP-A-S63-77150, patent document 2: JP-A-S63-102367, patent document 3: JP-A-S64-31457, and patent document 4: JP-A-2001-250953.
As stated above, the TFT substrate is manufactured by repeating a photolithography process composed of a sequential semiconductor process of ┌film formation→resist coating→exposure→development→etching→resist peeling┘ at least four times or five times or more. The photolithography process has a long procedure, and a CVD apparatus used for the film formation and an exposure apparatus used for the exposure are expensive, and therefore, there arises a problem that it becomes a rate-determining process in a production line. In order to efficiently increase the production quantity of the TFT substrate on investment, it is necessary that the number of times the photolithography process is repeated is decreased, so that the number of all processes is compressed and the process requiring the expensive apparatus, such as the CVD apparatus and the exposure apparatus, does not become a rate-determining process.